? semiconductor components industries, llc, 2010 june, 2010 -- rev. 2 1 publication order number: ntd4854n/d ntd4854n power mosfet 25 v, 128 a, single n--channel, dpak/ipak features ? trench technology ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? these are pb--free devices applications ? vcore applications ? dc--dc converters ? high/low side switching maximum ratings (t j =25 c unless otherwise stated) parameter symbol value unit drain--to--source voltage v dss 25 v gate--to--source voltage v gs 20 v continuous drain current r ja (note 1) steady state t a =25 c i d 20.8 a t a =85 c 16.1 power dissipation r ja (note 1) t a =25 c p d 2.5 w continuous drain current r ja (note 2) t a =25 c i d 15.7 a t a =85 c 12.2 power dissipation r ja (note 2) t a =25 c p d 1.43 w continuous drain current r jc (note 1) t c =25 c i d 128 a t c =85 c 99 power dissipation r jc (note 1) t c =25 c p d 93.75 w pulsed drain current t p =10 m s t a =25 c i dm 255 a current limited by package t a =25 c i dmaxpkg 45 a operating junction and storage temperature t j , t stg -- 5 5 t o +175 c source current (body diode) i s 78 a drain to source dv/dt dv/dt 6 v/ns single pulse drain--t o--source avalanche energy (t j =25 c, v dd =50v,v gs =10v, i l =26a pk ,l=1.0mh,r g =25 ) eas 338 mj lead temperature for soldering purposes (1/8? from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. f unctional operation above the recommended operating conditions is not implied. ex tended exposure to stresses above the recommended operating conditions may affect device reliability. marking diagrams & pin assignments http://onsemi.com v (br)dss r ds(on) max i d max 25 v 3.6 m @10v 128 a 4.7 m @4.5v g s n--channel mosfet d see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information yww 48 54ng 1 gate 2 drain 3 source 4 drain 4 drain 2 drain 1 gate 3 source 4 drain 2 drain 1 gate 3 source yww 48 54ng yww 48 54ng y = year ww = work week 4854n = device code g = pb--free package case 369aa dpak (bent lead) style 2 case 369d ipak (straight lead dpak) 1 2 3 4 1 2 3 4 case 369ac 3ipak (straight lead) 1 2 3 4
ntd4854n http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction--to--case (drain) r jc 1.6 c/w junction--to--tab (drain) r jc--tab 3.5 junction--to--ambient ? steady state (note 1) r ja 60 junction--to--ambient ? steady state (note 2) r ja 105 1. surface--mounted on fr4 board using 1 sq--in pad, 1 oz cu. 2. surface--mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j =25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain--to--source breakdown voltage v (br)dss v gs =0v,i d = 250 m a 25 v drain--to--source breakdown voltage temperature coefficient v (br)dss / t j 23 mv/ c zero gate voltage drain current i dss v gs =0v, v ds =20v t j =25 c 1.0 m a t j = 125 c 10 gate--to--source leakage current i gss v ds =0v,v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs =v ds ,i d = 250 m a 1.45 2.5 v negative threshold temperature coefficient v gs(th) /t j 6.0 mv/ c drain--to--source on resistance r ds(on) v gs =10v i d =30a 2.9 3.6 m v gs =4.5v i d =30a 3.6 4.7 forward transconductance g fs v ds =1.5v,i d =15a 122 s charges and capacitances input capacitance c iss v gs =0v,f=1.0mhz,v ds =12v 4600 pf output capacitance c oss 1100 reverse transfer capacitance c rss 578 total gate charge q g(tot) v gs =4.5v,v ds =15v,i d =30a 32.8 49.2 nc threshold gate charge q g(th) 3.7 gate--to--source charge q gs 11.8 gate--to--drain charge q gd 12.6 total gate charge q g(tot) v gs =10v,v ds =15v,i d =30a 65 nc switching characteristics (note 4) turn--on delay time t d(on) v gs =4.5v,v ds =15v, i d =15a,r g =3.0 22.6 ns rise time t r 40.7 turn--off delay time t d(off) 25 fall time t f 17.6 turn--on delay time t d(on) v gs =11.5v,v ds =15v, i d =15a,r g =3.0 12.1 ns rise time t r 17.6 turn--off delay time t d(off) 41 fall time t f 8.5 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntd4854n http://onsemi.com 3 electrical characteristics (t j =25 c unless otherwise specified) parameter unit max typ min test condition symbol drain--source diode characteristics forward diode voltage v sd v gs =0v, i s =30a t j =25 c 0.84 1.2 v t j = 125 c 0.71 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ m s, i s =30a 31.3 ns charge time t a 16 discharge time t b 15.3 reverse recovery charge q rr 20.2 nc package parasitic values source inductance l s t a =25 c 2.49 nh drain inductance, dpak l d 0.0164 drain inductance, ipak l d 1.88 gate inductance l g 3.46 gate resistance r g 0.6 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntd4854n http://onsemi.com 4 typical performance curves 10 v v ds , drain--to--source voltage (volts) i d , drain current (amps) v gs , gate--to--source voltage (volts) figure 1. on--region characteristics figure 2. transfer characteristics i d , drain current (amps) figure 3. on--resistance vs. gate--to--source voltage v gs , gate--to--source voltage (volts) figure 4. on--resistance vs. drain current and gate voltage i d , drain current (amps) r ds(on) , drain--to--source resistance ( ) r ds(on) , drain--to--source resistance ( ) figure 5. on--resistance variation with temperature t j , junction temperature ( c) figure 6. drain--to--source leakage current vs. drain voltage v ds , drain--to--source voltage (volts) r ds(on) , drain--to--source resistance (normalized) i dss , leakage (na) v ds 10 v t j =25 c t j =--55 c t j = 125 c v gs =4.5v v gs =0v i d =30a v gs =10v t j = 150 c t j = 125 c t j =25 c 3.8 v 3.0 v 3.6 v 2.8 v 3.2 v 3.4 v i d =30a t j =25 c v gs =11.5v t j =25 c 0 20 40 60 80 100 120 140 012345 160 0 20 40 60 80 100 120 140 123 45 160 180 200 0.002 0.006 0.010 0.014 0.020 246 810 0.002 0.0035 190 50 90 130 170 30 70 110 150 0.0025 0.004 0.003 0.005 0.6 0.8 1.0 1.2 1.4 --50 0 50 100 150 1.6 1.8 --25 25 75 125 175 100 1000 510152025 100000 0.004 0.008 0.012 0.016 1 10 t j =25 c 0.018 357 911 0.0045 10000
ntd4854n http://onsemi.com 5 typical performance curves c rss 01015 2.5 drain--to--source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 5 v gs =0v t j =25 c c oss c iss v gs figure 8. gate--to--source and drain--to--source voltage vs. total charge v gs , gate--to--source voltage (volts) q g , total gate charge (nc) i d =30a v dd =15v t j =25 c q 2 q 1 q t v sd , source--to--drain voltage (volts) i s , source current (amps) figure 9. resistive switching time variation vs. gate resistance r g , gate resistance (ohms) t, time (ns) v gs =0v figure 10. diode forward voltage vs. current t r t d(off) t d(on) t f v dd =10v i d =15a v gs =10v t j =25 c figure 11. maximum rated forward biased safe operating area v ds , drain--to--source voltage (volts) i d , drain current (amps) r ds(on) limit thermal limit package limit v gs =20v single pulse t c =25 c 1ms 100 m s 10 ms dc 10 m s 20 t j , junction temperature ( c) i d =26a figure 12. maximum avalanche energy vs. starting junction temperature eas, single pulse drain--to--source avalanche energy (mj) 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 04060 20 80 0 2 4 6 8 10 12 30 50 10 70 1 10 100 1 10 100 1000 0.5 0.7 0 10 20 30 5 15 25 0.6 0.9 0.1 10 100 1 10 100 1000 0.1 1 25 125 175 80 120 160 40 0 75 280 320 360 240 200 100 150 50 7.5 12.5 17.5 5500 6000 0.8
ntd4854n http://onsemi.com 6 typical performance curves figure 13. thermal response r(t), effective transient thermal resistance (normalized) t, time ( m s) 0.1 1.0 0.01 0.1 0.2 0.02 d=0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) -- t c =p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+00 1.0e+01 1.0e--01 1.0e--02 1.0e--03 1.0e--04 1.0e--05 ordering information device package shipping ? ntd4854nt4g dpak (pb--free) 2500 / tape & reel ntd4854n--1g ipak (pb--free) 75 units / rail ntd4854n--35g ipak trimmed lead (3.5 ? 0.15 mm) (pb--free) 75 units / rail ?for information on tape and reel specificat ions, including part orientation and tape si zes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd4854n http://onsemi.com 7 package dimensions dpak (single guage) case 369aa--01 issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 -- -- -- 0 . 0 4 0 -- -- -- 1 . 0 1 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ------ 3.93 ------ notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within dimensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 ? mm inches ? scale 3:1 *for additional information on our pb--free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ntd4854n http://onsemi.com 8 package dimensions 3 ipak, straight lead case 369ac--01 issue o d a k b r v f g 3pl e c j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.043 0.94 1.09 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.134 0.142 3.40 3.60 r 0.180 0.215 4.57 5.46 v 0.035 0.050 0.89 1.27 w 0.000 0.010 0.000 0.25 notes: 1.. dimensioning and tolerancing per ansi y14.5m, 1982. 2.. controlling dimension: inch. 3. seating plane is on top of dambar position. 4. dimension a does not include dambar position or mold gate. w seating plane 0.13 (0.005) w style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k -- t -- seating plane r b f g d 3pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ------ 3.93 ------ ipak (straight lead dpak) case 369d--01 issue b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation speci al, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each custo mer application by customer?s technical experts. scillc does not conve y any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant int o the body, or other applications intended to support or sustain life, or for any other application in which the f ailure of the scillc product could create a situation where personal inj ury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthoriz ed application, buyer shall indemnify and hold scillc and its officers, em ployees, subsidiaries, affiliates, and distributors harmless against all claims, cos ts, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, an y claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the p art. scillc is an equal opportunity/affirmative action employer. this literature is subj ect to all applicable copyright la ws and is not for resale in any manner. publication ordering information n. american technical support : 800--282--9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81--3--5773--3850 ntd4854n/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303--675--2175 or 800--344--3860 toll free usa/canada fax : 303--675--2176 or 800--344--3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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